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DATA SHEET
8GB Registered DDR3 SDRAM DIMM
EBJ82HF4B1RA (1024M words x 72 bits, 4 Ranks)
Specifications
* Density: 8GB * Organization 1024M words x 72 bits, 4 ranks * Mounting 36 pieces of 2G bits DDR3 SDRAM with DDP (FBGA) DDP: 2 pieces of 1G bits chips sealed in one package * Package: 240-pin socket type dual in line memory module (DIMM) PCB height: 30.5mm (max.) Lead pitch: 1.0mm Lead-free (RoHS compliant) * Power supply: VDD = 1.5V 0.075V * Data rate: 1066Mbps/800Mbps (max.) * Eight internal banks for concurrent operation (components) * Interface: SSTL_15 * Burst lengths (BL): 8 and 4 with Burst Chop (BC) * /CAS Latency (CL): 6, 7, 8 * /CAS write latency (CWL): 5, 6 * Precharge: auto precharge option for each burst access * Refresh: auto-refresh, self-refresh * Refresh cycles Average refresh period 7.8s at 0C TC +85C 3.9s at +85C < TC +95C * Operating case temperature range TC = 0C to +95C
Features
* Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS * Posted /CAS by programmable additive latency for better command and data bus efficiency * On-Die-Termination (ODT) for better signal quality Synchronous ODT Dynamic ODT Asynchronous ODT * Multi Purpose Register (MPR) for temperature read out * ZQ calibration for DQ drive and ODT * Programmable Partial Array Self-Refresh (PASR) * /RESET pin for Power-up sequence and reset function * SRT range: Normal/extended Auto/manual self-refresh * Programmable Output driver impedance control * 2 piece of registering clock driver and 1 piece of serial EEPROM (256 bytes EEPROM) for Presence Detect (PD) * Class B temperature sensor functionality with EEPROM Note: Warranty void if removed DIMM heat spreader.
Document No. E1306E30 (Ver. 3.0) Date Published December 2008 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2008
EBJ82HF4B1RA
Ordering Information
Component 1 JEDEC speed bin* Data rate Mbps(max.) (CL-tRCD-tRP) 1066 800 DDR3-1066F (7-7-7) DDR3-800E (6-6-6) Contact pad Gold
Part number EBJ82HF4B1RA-AE-E EBJ82HF4B1RA-8C-E
Package 240-pin DIMM (lead-free)
Mounted devices 2G bits DDR3 SDRAM*
2
Notes: 1. Module /CAS latency = component CL + 1. 2. Please refer to 1Gb DDR3 datasheet (E1128E) for electrical characteristics.
Data Sheet E1306E30 (Ver. 3.0)
2
EBJ82HF4B1RA
Pin Configurations
Front side 1 pin 48 pin 49 pin 120 pin
121 pin
168 pin 169 pin Back side
240 pin
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Pin name VREFDQ VSS DQ0 DQ1 VSS /DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS /DQS1 DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS /DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS /DQS3 DQS3 VSS DQ26
Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
Pin name A2 VDD CK1 /CK1 VDD VDD VREFCA Par_In VDD A10(AP) BA0 VDD /WE /CAS VDD /CS1 ODT1 VDD /CS2 VSS DQ32 DQ33 VSS /DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS /DQS5 DQS5 VSS DQ42
Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
Pin name VSS DQ4 DQ5 VSS DQS9 /DQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DQS10 /DQS10 VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DQS11 /DQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS12 /DQS12 VSS DQ30 DQ31
Pin No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216
Pin name A1 VDD VDD CK0 /CK0 VDD /EVENT A0 VDD BA1 VDD /RAS /CS0 VDD ODT0 A13 VDD /CS3 VSS DQ36 DQ37 VSS DQS13 /DQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS14 /DQS14 VSS DQ46 DQ47
Data Sheet E1306E30 (Ver. 3.0)
3
EBJ82HF4B1RA
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin name DQ27 VSS CB0 CB1 VSS /DQS8 DQS8 VSS CB2 CB3 VSS VTT VTT CKE0 VDD BA2 /Err_Out VDD A11 A7 VDD A5 A4 VDD Pin No. 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin name DQ43 VSS DQ48 DQ49 VSS /DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS /DQS7 DQS7 VSS DQ58 DQ59 VSS SA0 SCL SA2 VTT Pin No. 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Pin name VSS CB4 CB5 VSS DQS17 /DQS17 VSS CB6 CB7 VSS NC /RESET CKE1 VDD A15 A14 VDD A12 A9 VDD A8 A6 VDD A3 Pin No. 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Pin name VSS DQ52 DQ53 VSS DQS15 /DQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS16 /DQS16 VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT
Data Sheet E1306E30 (Ver. 3.0)
4
EBJ82HF4B1RA
Pin Description
Pin name A0 to A15 A10 (AP) A12 (/BC) BA0, BA1, BA2 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /CS0, /CS1, /CS2, /CS3 CKE0, CKE1 CK0, CK1 /CK0, /CK1 DQS0 to DQS17, /DQS0 to /DQS17 SCL SDA SA0, SA1, SA2 VDD VDDSPD VREFCA VREFDQ VSS VTT /RESET ODT0, ODT1 Par_In /Err_Out /Event NC Function Address input Row address Column address Auto precharge Burst chop Bank select address Data input/output Check bit (Data input/output) Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Reference voltage for CA Reference voltage for DQ Ground Termination Voltage Set DRAM to known state ODT control Parity bit for the Address and Control bus Parity error found on the Address and Control bus Temperature event pin No connection A0 to A13 A0 to A9, A11
Data Sheet E1306E30 (Ver. 3.0)
5
EBJ82HF4B1RA
Serial PD Matrix
Byte No. Function described 0 1 2 3 4 5 6 7 8 9 10 11 12 Number of serial PD bytes written/SPD device size/CRC coverage SPD revision Key byte/DRAM device type Key byte/module type SDRAM density and banks SDRAM addressing Module nominal voltage, VDD Module organization Module memory bus width Fine timebase (FTB) dividend/divisor Medium timebase (MTB) dividend Medium timebase (MTB) divisor SDRAM minimum cycle time (tCK (min.)) -AE -8C 13 14 Reserved SDRAM /CAS latencies supported, LSB -AE -8C 15 16 SDRAM /CAS latencies supported, MSB SDRAM minimum /CAS latencies time (tAA (min.)) -AE -8C 17 18 SDRAM write recovery time (tWR) SDRAM minimum /RAS to /CAS delay (tRCD) -AE -8C 19 Bit7 Bit6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 1 Bit5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 0 1 0 1 1 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 1 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 1 1 0 1 0 1 0 0 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 1 1 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 92H 10H 0BH 01H 02H 12H 00H 18H 0BH 52H 01H 08H 0FH 14H 00H 1CH 04H 00H 69H 78H 78H 69H 78H 3CH 50H 69H 78H 11H 2CH 95H A4H 70H 37.5ns 50.625ns 52.5ns 110ns Comments 176/256/0-116 Revision 1.0 DDR3 SDRAM Registered 1G bits, 8 banks 14 rows, 11 columns 1.5V 4 ranks/x4 bits 72 bits/ECC 5/2 1 8 1.875ns 2.5ns -- CL = 6, 7, 8 CL = 6 -- 13.125ns 15ns 15ns 13.125ns 15ns 7.5ns 10ns 13.125ns 15ns
SDRAM minimum row active to row active delay (tRRD) 0 -AE -8C 0 0 0 0 SDRAM minimum row precharge time (tRP) -AE -8C
20
21 22 23
SDRAM upper nibbles for tRAS and tRC
SDRAM minimum active to precharge time 0 (tRAS), LSB SDRAM minimum active to active /autorefresh time (tRC), LSB 1 -AE -8C 1 0 SDRAM minimum refresh recovery time delay (tRFC), LSB
24
Data Sheet E1306E30 (Ver. 3.0)
6
EBJ82HF4B1RA
Byte No. Function described 25 26 27 28 29 SDRAM minimum refresh recovery time delay (tRFC), MSB SDRAM minimum internal write to read command delay (tWTR) SDRAM minimum internal read to precharge command delay (tRTP) Upper nibble for tFAW Minimum four activate window delay time (tFAW) -AE -8C 30 31 32 33 SDRAM output drivers supported SDRAM refresh options Module thermal sensor SDRAM device type
Bit7 Bit6 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
Bit5 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 03H 3CH 3CH 01H 2CH 40H 83H 81H 80H 80H 00H 10H 33H 05H 0AH 80H 04H 80H B3H 97H 03H 1DH 00H 00H 50H 50H 00H 00H 00H 00H 00H 00H
Comments 110ns 7.5ns 7.5ns 37.5ns 37.5ns 40ns DLL-off, RZQ/6, 7 PASR/2X refresh rate at +85C to +95C Incorporated Non standard -- 30 < height 31mm
34 to 59 Reserved 60 61 62 63 64 65 Module nominal height Module maximum thickness Reference raw card used DIMM module attributes Heat spreader solution Register vender ID (LSB) (Inphi) (TI) 66 Register vender ID (MSB) (Inphi) (TI) 67 Register revision (Inphi) (TI) 68 69 70 71 72 73 74 75 76 77 to 116 Register type Register control word function (RC0, 1) Register control word function (RC2, 3) Register control word function (RC4, 5) Register control word function (RC6, 7) Register control word function (RC8, 9)
Raw card F 2row/2register Incorporated Naming bank=5 Naming bank=1 Actual ID
Rev.4 Rev. 3.1 SSTE32882 Default Default Default Default Default Default Default Default --
Register control word function (RC10, 11) 0 Register control word function (RC12, 13) 0 Register control word function (RC14, 15) 0 Module specific section 0
Data Sheet E1306E30 (Ver. 3.0)
7
EBJ82HF4B1RA
Byte No. Function described 117 118 119 120 121 122 to 125 126 Module ID: manufacturer's JEDEC ID code, LSB Module ID: manufacturer's JEDEC ID code, MSB Module ID: manufacturing location Module ID: manufacturing date Module ID: manufacturing date Module ID: module serial number Cyclical redundancy code (CRC) -AE (Inphi) (TI) -8C (Inphi) (TI) 127 Cyclical redundancy code (CRC) -AE (Inphi) (TI) -8C (Inphi) (TI) 128 129 130 131 132 133 134 135 136 137 138 139 140 141 Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number -AE -8C 142 Module part number -AE -8C 143 144 145 146 147 Module part number Module part number Module part number Module revision code Module revision code
Bit7 Bit6 0 1 x x x x 0 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x x x x 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 0 0
Bit5 0 1 x x x x 1 1 1 1 0 1 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 1 1
Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 0 1 x x x x 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 1 x x x x 0 1 1 0 1 0 0 1 0 0 1 1 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 x x x x 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 0 0 1 1 x x x x 1 0 1 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 x x x x 1 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 1 1 0 0 0 02H FEH xx xx xx xx 67H F8H FFH 60H CCH B1H 95H E8H 45H 42H 4AH 38H 32H 48H 46H 34H 42H 31H 52H 41H 2DH 41H 38H 45H 43H 2DH 45H 20H 30H 20H
Comments Elpida Memory Elpida Memory
Year code (BCD) Week code (BCD)
E B J 8 2 H F 4 B 1 R A -- A 8 E C -- E (Space) Initial (Space)
Data Sheet E1306E30 (Ver. 3.0)
8
EBJ82HF4B1RA
Byte No. Function described 148 149 150 to 175 176 to 255 SDRAM manufacturer's JEDEC ID code, LSB SDRAM manufacturer's JEDEC ID code, MSB Manufacturer's specific data Open for customer use
Bit7 Bit6 0 1 0 0 1 0
Bit5 0 1 0
Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 0 1 0 0 1 0 0 1 0 1 1 0 0 0 0 02H FEH 00H
Comments Elpida Memory Elpida Memory
Data Sheet E1306E30 (Ver. 3.0)
9
Block Diagram
DQS1
DQS2
DQS3
/DQS1
/DQS2
/DQS3
DQS0 VSS VSS VSS VSS
DQS8
DQ16 to DQ19
DQ24 to DQ27
CB0 to CB3
DQ8 to DQ11
/DQS0 4 4 4 4
/DQS8
VSS
Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1
Rs6 Rs6 Rs6 Rs6
DQ0 to DQ3 4
Rs1
Rs6
Data Sheet E1306E30 (Ver. 3.0)
DM DM DM DM DM DQS DQS DQS DQS DQS
/CS Command CK Command CK Command CK Command CK /CS /CS /CS /ARCS0_A
Rs3
/CS
/DQS
/DQS
/DQS
/DQS
/DQS
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
VTT
Rs3
3
VDD
Rs4
Command CK
/ARcommand_A APCK0_A
D0
D1
D2
D3
D8
/CK /CK CKE ODT ODT ODT Address, BA
Rs6 Rs6
/CK CKE Address, BA CKE CKE
/CK
/CK
/APCK0_A ARCKE0_A ARODT0_A
0.1F
Rs3
Rs3
CKE Address, BA
Rs6
VTT
Rs6
17
Rs3
ODT Address, BA
ODT Address, BA
Rs6
AR[Address,BA]_A
DM DM DM DM DQS DQS DQS
DM
DQS
DQS
/DQS
/DQS
/DQS
/DQS
/DQS
Rs3
DQ0 to DQ3 ZQ DQ0 to DQ3 ZQ DQ0 to DQ3 ZQ DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
/ARCS1_A
VTT
D19
D20
D18
D21
D26
Rs3
Block Diagram (1)
10
Rs6 Rs6 Rs6
/CS Command CK /CK CKE ODT Address, BA /CS Command CK /CK CKE ODT Address, BA
Rs6
/CS Command CK /CK CKE ODT Address, BA
/CS Command CK /CK CKE ODT Address, BA
/CS Command CK /CK CKE ODT Address, BA
ARCKE1_A VDD
Rs6
Rs3
DM DM DM
DM
DM
DQS
DQS
DQS
DQS
DQS
/CS /CS Command CK CK Command /CK CKE ODT Address, BA
Rs6 Rs6
/CS
/CS
/CS Command CK CK
/BRCS2_A
/DQS
/DQS
/DQS
/DQS
/DQS
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
VTT
Rs3
3
Command /CK CKE ODT Address, BA
Rs6
/BRcommand_A BPCK0_A /CK CKE ODT Address, BA
Rs6
VDD
Rs4
Command CK
D37
D38
D36
/CK CKE ODT Address, BA
D39
D44
0.1F
Rs6
Rs3
/CK CKE
/BPCK0_A BRCKE0_A BRODT1 _A
Rs3
VTT DM DM DQS DQS /DQS /DQS DQ0 to DQ3 ZQ DQ0 to DQ3 ZQ
Rs3
ODT
17
Address, BA
BR[Address,BA]_A
DM
DM
DM
DQS
DQS
DQS
/DQS
/DQS
/DQS
Rs3
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
/BRCS3_A
EBJ82HF4B1RA
VTT
D55
D56
D54
D57
D62
Rs3
/CS Command CK /CK CKE ODT Address, BA /CS Command CK /CK CKE ODT Address, BA
/CS Command CK /CK CKE ODT Address, BA
/CS Command CK /CK CKE ODT Address, BA
/CS Command CK /CK CKE ODT Address, BA
BRCKE1_A VDD
DQS17
DQS10
DQS11
DQS12
/DQS17
/DQS10
/DQS11
/DQS12
DQS9 VSS VSS VSS VSS
CB4 to CB7
DQ12 to DQ15
DQ20 to DQ23
DQ28 to DQ31
/DQS9 4 4 4 4
VSS
Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1
Rs6 Rs6 Rs6 Rs6
DQ4 to DQ7 4
Rs1
Rs6
Data Sheet E1306E30 (Ver. 3.0)
DM DM DM DM DM DQS DQS DQS DQS DQS /DQS /DQS /DQS /DQS /DQS
/CS Command CK /CS /CS /CS /CS /ARCS0_A
Rs3
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
VTT
Rs3
3
VDD
Rs4
D9
/CK CKE ODT Address, BA ODT Address, BA
Rs6 Rs6 Rs6 Rs6
Command CK /CK
Command CK /CK
Command CK /CK
Command CK /CK CKE
/ARcommand_A APCK1_A /APCK1_A
D10
D11
D12
D17
Rs3
0.1F VTT
Rs3
CKE ODT Address, BA ODT Address, BA
CKE
CKE
ARCKE0_A
17
Rs3
ODT Address, BA
Rs6
ARODT0_A AR[Address,BA]_A
DM
DM
DM
DM
DQS
DQS
DQS
DQS
/DQS
/DQS
/DQS
/DQS
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DM
DQS
/DQS
Rs3
DQ0 to DQ3 ZQ
/ARCS1_A
VTT
D28
D29
D30
D27
D35
Rs3
/CS Command CK /CK CKE /CS Command CK /CK CKE ODT Address, BA Address, BA
Rs6 Rs6
Block Diagram (2)
11
ODT Address, BA
Rs6
/CS Command CK /CK CKE ODT Address, BA
Rs6
/CS Command CK /CK CKE ODT
/CS Command CK /CK CKE ODT
ARCKE1_A VDD Address, BA
Rs6
DM
DM
DM
DM
DQS
DQS
DQS
DQS
/DQS
/DQS
/DQS
/DQS
DM
DQS
/DQS
Rs3
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
/CS Command CK Command CK /CK CKE ODT Address, BA
Rs6
VTT
Command CK /CK
Rs3
/CS /CS
/CS
/CS
/BRCS2_A
3
VDD
Rs4
D46
D47
D48
D45
/CK CKE ODT Address, BA
Rs6
Command CK /CK CKE
Command CK /CK CKE
/BRcommand_A BPCK1_A
D53
/BPCK1_A BRCKE0_A ODT Address, BA
Rs6
Rs3
CKE ODT Address, BA
Rs6
Rs3
0.1F VTT
17
Rs3
ODT Address, BA
Rs6
BRODT1 _A BR[Address,BA]_A
DM
DM
DM
DM
DM
DQS
DQS
DQS
DQS
/DQS
/DQS
/DQS
/DQS
DQS
/DQS
Rs3
/CS /CS Command CK /CK CKE ODT Address, BA Command CK
/CS
/CS Command
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
/CS
DQ0 to DQ3 ZQ
/BRCS3_A
EBJ82HF4B1RA
VTT
D64
D65
D66
D63
D71
Rs3
/CK CKE ODT Address, BA
CK /CK CKE
Command CK /CK CKE ODT Address, BA
Command CK /CK CKE ODT Address, BA
BRCKE1_A ODT Address, BA VDD
DQS7 DQS4 VSS VSS VSS
DQS6
DQS5
/DQS7 /DQS4 4 4 4
/DQS6
/DQS5
VSS
Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1
Rs6 Rs6 Rs6
DQ56 to DQ59 DQ32 to DQ35 4
Rs1
Rs6 Rs3
DQ48 to DQ51
/ARCS0_B
DQ40 to DQ43
DM
/CS /CS /CS
DM
DM
DM
DQS
DQS
DQS
DQS
/DQS
/DQS
/DQS
/DQS
/CS
Rs3
3
VTT
Data Sheet E1306E30 (Ver. 3.0)
DQ0 to DQ3 ZQ DQ0 to DQ3 ZQ DQ0 to DQ3 ZQ DQ0 to DQ3 ZQ
Rs4
VDD
Command CK /CK
Command CK /CK
Command CK /CK Command CK /CK CKE ODT Address, BA
Rs6
/ARcommand_B APCK0_B /APCK0_B
D5
D4
D7
D2
Rs3
CKE CKE ODT Address, BA Address, BA
Rs6 Rs6 Rs3 Rs3
0.1uF VTT
ODT Address, BA
Rs6
CKE ODT
ARCKE0_B ARODT0_B
17
AR[Address,BA]_B
DM
DM
DM
DM
DQS
DQS
DQS
DQS
/DQS
/DQS
/DQS
/DQS
Rs3
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
/ARCS1_B
VTT
D25
D20
D23
D22
Rs3
Block Diagram (3)
12
Rs6 Rs3 Rs6 Rs6
/CS Command CK /CK CKE ODT Address, BA
/CS Command CK /CK CKE ODT Address, BA
/CS Command CK /CK CKE ODT Address, BA
/CS Command CK /CK CKE ODT Address, BA
ARCKE1_B VDD
Rs6
DM
/CS Command CK
DM
DM
DM
DQS
DQS
DQS
DQS
/DQS
/DQS
/DQS
/DQS
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
/CS
DQ0 to DQ3 ZQ
/CS Command CK
VTT
Rs3 Rs4
/CS Command CK
/BRCS2_B
3
Command CK
/BRcommand_B BPCK0_B
VDD
D43
D42
D41
D40
Rs3
/CK /CK CKE ODT Address, BA
Rs6
/CK CKE
/CK CKE ODT Address, BA
Rs6
/BPCK0_B BRCKE0_B BRODT1 _B
CKE
Rs3
0.1F VTT
ODT Address, BA
Rs6
17
Rs3
ODT Address, BA
Rs6
BR[Address,BA]_B
DM
DM
DM
DM
DQS
DQS
DQS
DQS
/DQS
/DQS
/DQS
/DQS
Rs3
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
/BRCS3_B
EBJ82HF4B1RA
VTT
D61
D60
D59
D58
Rs3
/CS Command CK /CK CKE ODT Address, BA
/CS Command CK /CK CKE ODT Address, BA
/CS Command CK /CK CKE ODT Address, BA
/CS Command CK /CK CKE ODT Address, BA
BRCKE1_B VDD
DQS13
/DQS13
DQS16 VSS VSS VSS
DQS15
DQS14
/DQS16 4 4 4
/DQS15
/DQS14
DQ36 to DQ39
VSS
Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1
Rs6 Rs6 Rs6
DQ60 to DQ63 4
Rs1
Rs6 Rs3
DQ52 to DQ55
/ARCS0_B
DQ44 to DQ47
DM
/CS /CS /CS
DM
DM
DM
DQS
DQS
DQS
DQS
/DQS
/DQS
/DQS
/DQS
/CS
Rs3
3
VTT
Data Sheet E1306E30 (Ver. 3.0)
DQ0 to DQ3 ZQ DQ0 to DQ3 ZQ DQ0 to DQ3 ZQ DQ0 to DQ3 ZQ
Rs4
VDD
Command CK /CK
Command CK /CK
Command CK /CK Command CK /CK CKE ODT Address, BA
Rs6
/ARcommand_B APCK1_B /APCK1_B
D14
D13
D16
D15
Rs3
CKE CKE ODT Address, BA Address, BA
Rs6 Rs6 Rs3 Rs3
0.1F VTT
ODT Address, BA
Rs6
CKE ODT
ARCKE0_B ARODT0_B
17
AR[Address,BA]_B
DM
DM
DM
DM
DQS
DQS
DQS
DQS
/DQS
/DQS
/DQS
/DQS
Rs3
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
/ARCS1_B
VTT
D34
D33
D32
D31
Rs3
Block Diagram (4)
13
Rs6 Rs3 Rs6 Rs6
/CS Command CK /CK CKE ODT Address, BA
/CS Command CK /CK CKE ODT Address, BA
/CS Command CK /CK CKE ODT Address, BA
/CS Command CK /CK CKE ODT Address, BA
ARCKE1_B VDD
Rs6
DM
/CS Command CK
DM
DM
DM
DQS
DQS
DQS
DQS
/DQS
/DQS
/DQS
/DQS
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
/CS
DQ0 to DQ3 ZQ
/CS Command CK
VTT
Rs3 Rs4
/CS Command CK
/BRCS2_B
3
Command CK
/BRcommand_B BPCK1_B
VDD
D52
D51
D50
D49
Rs3
/CK /CK CKE ODT Address, BA
Rs6
/CK CKE
/CK CKE ODT Address, BA
Rs6
/BPCK1_B BRCKE0_B BRODT1 _B
CKE
Rs3 Rs3
0.1F VTT
ODT Address, BA
Rs6
17
ODT Address, BA
Rs6
BR[Address,BA]_B
DM
DM
DM
DM
DQS
DQS
DQS
DQS
/DQS
/DQS
/DQS
/DQS
Rs3
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
DQ0 to DQ3 ZQ
/BRCS3_B
EBJ82HF4B1RA
VTT
D70
D69
D68
D67
Rs3
/CS Command CK /CK CKE ODT Address, BA
/CS Command CK /CK CKE ODT Address, BA
/CS Command CK /CK CKE ODT Address, BA
/CS Command CK /CK CKE ODT Address, BA
BRCKE1_B VDD
EBJ82HF4B1RA
/CS0*2 /CS1*2 BA Address Command CKE0 CKE1 ODT0
RS2
RS2
/ARCS0_A -> /CS: SDRAMs D0 to D3, D8 to D12, D17 /ARCS0_B -> /CS: SDRAMs D4 to D7, D13 to D16
/ARCS1_A -> /CS: SDRAMs D18 to D21, D26 to D30, D35 /ARCS1_B -> /CS: SDRAMs D22 to D25, D31 to D34
ARBA_A -> BA0 to BA2: SDRAMs D0 to D3, D8 to D12, D17 to D21, D26 to D30, D35 ARBA_B -> BA0 to BA2: SDRAMs D4 to D7, D13 to D16, D22 to D25, D31 to D34 ARAddress_A -> A0 to A13: SDRAMs D0 to D3, D8 to D12, D17 to D21, D26 to D30, D35 ARAddress_B -> A0 to A13: SDRAMs D4 to D7, D13 to D16, D22 to D25, D31 to D34 ARCommand_A -> /RAS, /CAS, /WE: SDRAMs D0 to D3, D8 to D12, D17 to D21, D26 to D30, D35 ARCommand_B -> /RAS, /CAS, /WE: SDRAMs D4 to D7, D13 to D16, D22 to D25, D31 to D34
RS2
RS2
RS2
RS2
RS2
RS2
R E G I S T E R / P L L
A
ARCKE0_A -> CKE1: SDRAMs D0 to D3, D8 to D12, D17 ARCKE0_B -> CKE1: SDRAMs D4 to D7, D13 to D16 ARCKE1_A -> CKE0: SDRAMs D18 to D21, D26 to D30, D35 ARCKE1_B -> CKE0: SDRAMs D22 to D25, D31 to D34 ARODT0_A -> ODT1: SDRAMs D0 to D3, D8 to D12, D17 ARODT0_B -> ODT1: SDRAMs D4 to D7, D13 to D16 APCK0_A -> CK: APCK0_B -> CK: APCK1_A -> CK: APCK1_B -> CK: /APCK0_A -> /CK: /APCK0_B -> /CK: /APCK1_A -> /CK: /APCK1_B -> /CK: /Err_Out SDRAMs D0 to D3, D8, D18 to D21, D26 SDRAMs D4 to D7, D22 to D25 SDRAMs D9 to D12, D17, D27 to D30, D35 SDRAMs D13 to D16, D31 to D34 SDRAMs D0 to D3, D8, D18 to D21, D26 SDRAMs D4 to D7, D22 to D25 SDRAMs D9 to D12, D17, D27 to D30, D35 SDRAMs D13 to D16, D31 to D34
CK0
RS5
/CK0
Par_In
RS2
/RESET
/RESET
/RESET: SDRAMs D0 to D71
Block Diagram (5)
Data Sheet E1306E30 (Ver. 3.0)
14
EBJ82HF4B1RA
/CS2*2 /CS3*2 BA Address Command CKE0 CKE1 ODT0
R S2
R S2
/BRCS2_A -> /CS: SDRAMs D36 to D39, D44 to D48, D53 /BRCS2_B -> /CS: SDRAMs D40 to D43, D49 to D52
/BRCS3_A -> /CS: SDRAMs D54 to D57, D62 to D66, D71 /BRCS3_B -> /CS: SDRAMs D58 to D61, D67 to D70
BRBA_A -> BA0 to BA2: SDRAMs D36 to D39, D44 to D48, D53 to D57, D62 to D66, D71 BRBA_B -> BA0 to BA2: SDRAMs D40 to D43, D49 to D52, D58 to D61, D67 to D70 BRAddress_A -> A0 to A13: SDRAMs D36 to D39, D44 to D48, D53 to D57, D62 to D66, D71 BRAddress_B -> A0 to A13: SDRAMs D40 to D43, D49 to D52, D58 to D61, D67 to D70 BRCommand_A -> /RAS, /CAS, /WE: SDRAMs D36 to D39, D44 to D48, D53 to D57, D62 to D66, D71 BRCommand_B -> /RAS, /CAS, /WE: SDRAMs D40 to D43, D49 to D52, D58 to D61, D67 to D70
R S2
R S2
R S2
R S2
R S2
R S2
R E G I S T E R / P L L
B
BRCKE0_A -> CKE1: SDRAMs D36 to D39, D44 to D48, D53 BRCKE0_B -> CKE1: SDRAMs D40 to D43, D49 to D52 BRCKE1_A -> CKE0: SDRAMs D54 to D57, D62 to D66, D71 BRCKE1_B -> CKE0: SDRAMs D58 to D61, D67 to D70 BRODT1_A -> ODT1: SDRAMs D36 to D39, D44 to D48, D53 BRODT1_B -> ODT1: SDRAMs D40 to D43, D49 to D52 BPCK0_A -> CK: BPCK0_B -> CK: BPCK1_A -> CK: BPCK1_B -> CK: SDRAMs D40 to D43, D58 to D61 SDRAMs D36 to D39, D44, D54 to D57, D62 SDRAMs D45 to D48, D53, D63 to D66, D71 SDRAMs D49 to D52, D67 to D70
CK0
RS5
/CK0
/BPCK0_A -> /CK: SDRAMs D40 to D43, D58 to D61 /BPCK0_B -> /CK: SDRAMs D36 to D39, D44, D54 to D57, D62 /BPCK1_A -> /CK: SDRAMs D45 to D48, D53, D63 to D66, D7 /BPCK1_B -> /CK: SDRAMs D49 to D52, D67 to D70
Par_In
RS2
/Err_Out
/RESET
/RESET
/RESET: SDRAMs D0 to D71
Note: 1. DQ wiring may be changed within a nibble.
RS5
CK1
/CK1 VTT VDDSPD VREFCA VREFDQ VDD
Terminated at near card edge
* D0 to D71: 1G bits DDR3 SDRAM Address, BA: A0 to A15, BA0 to BA2 Command: /RAS, /CAS, /WE U1: 256 bytes EEPROM Rs1: 15 Rs2: 22 Rs3: 36 Rs4: 30 Rs5: 120 Rs6: 240 Register: SSTE32882
SPD SDRAMs (D0 to D71) SDRAMs (D0 to D71) SDRAMs (D0 to D71)
SDRAMs (D0 to D71), SPD
VSS
Serial PD
SCL
SA0
SA1 SA2
SCL SDA
SDA
A0
U1
A1 A2 /EVENT
/EVENT
Block Diagram (6)
Data Sheet E1306E30 (Ver. 3.0)
15
EBJ82HF4B1RA
VTT
D45 D63
D36 D27 D54
D46 D64 D37 D55
D47 D65 D38 D56
D48 D66 D39 D57
D53 D71 D44 D62
D49 D67 D40 D58
D50 D68 D41 D59
D51 D69 D42 D60
D52 D70 D43 D61
VTT
Register
VTT
D0 D18 D9 D27
D1 D19 D10 D28
D2 D20 D11 D29
D3 D21 D12 D30
D8 D26 D17 D35
D4 D22 D13 D31
D5 D23 D14 D32
D6 D24 D15 D33
D7 D25 D16 D34
VTT
Address, command and control line
1. Unused register inputs ODT1 for Register A and ODT0 for Register B are tied to ground.
Block Diagram (7)
Data Sheet E1306E30 (Ver. 3.0)
16
VTT
VTT
Register
VTT
VTT
EBJ82HF4B1RA
Electrical Specifications
* All voltages are referenced to VSS (GND). Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Output voltage Reference voltage Reference voltage for DQ Storage temperature Power dissipation Short circuit output current Symbol VDD VIN VOUT VREFCA VREFDQ Tstg PD IOUT Value -0.4 to +1.975 -0.4 to +1.975 -0.4 to +1.975 -0.4 to 0.6 x VDD -0.4 to 0.6 x VDDQ -55 to +100 18 50 Unit V V V V V C W mA 1, 4 Notes 1, 3, 4 1, 4 1, 4 3, 4 3, 4 1, 2, 4
Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage temperature is the case surface temperature on the center/top side of the DRAM. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. 4. DDR3 SDRAM component specification. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Operating Temperature Condition
Parameter Operating case temperature Symbol TC Rating 0 to +95 Unit C Notes 1, 2, 3
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0C to +85C under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between +85C and +95C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9s. (This double refresh requirement may not apply for some devices.) b) If Self-refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 bit [A6, A7] = [0, 1]) or enable the optional Auto Self-Refresh mode (MR2 bit [A6, A7] = [1, 0]).
Data Sheet E1306E30 (Ver. 3.0)
17
EBJ82HF4B1RA
Recommended DC Operating Conditions (TC = 0C to +85C)
Parameter Supply voltage Symbol VDD, VDDQ VSS VDDSPD Input reference voltage Input reference voltage for DQ Termination voltage VREFCA (DC) VREFDQ (DC) VTT min. 1.425 0 3.0 0.49 x VDDQ 0.49 x VDDQ VDDQ/2 - TBD typ. 1.5 0 3.3 max. 1.575 0 3.6 Unit V V V V V V 1, 4, 5 1, 4, 5 Notes 1, 2, 3 1
0.50 x VDDQ 0.51 x VDDQ 0.50 x VDDQ 0.51 x VDDQ TBD VDDQ/2 + TBD
Notes: 1. 2. 3. 4.
DDR3 SDRAM component specification. Under all conditions VDDQ must be less than or equal to VDD. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than 1% VDD (for reference: approx 15 mV). 5. For reference: approx. VDD/2 15 mV.
Data Sheet E1306E30 (Ver. 3.0)
18
EBJ82HF4B1RA
DC Characteristics 1 (TC = 0C to +85C, VDD = 1.5V 0.075V, VSS = 0V)
Parameter Operating current (ACT-PRE) Operating current (ACT-READ-PRE) Precharge power-down standby current IDD2PS Precharge quiet standby current Precharge standby current Active power-down current (Always fast exit) Active standby current Operating current (Burst read operating) Operating current (Burst write operating) Burst refresh current Self-refresh current normal temperature range All bank interleave read current IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7R 1066 800 Symbol IDD0 IDD1 IDD2PF Data rate (Mbps) 1066 800 1066 800 1066 800 1066 800 1066 800 1066 800 1066 800 1066 800 1066 800 1066 800 1066 800 max. 4340 4030 4610 4310 2810 2720 2810 2720 3910 3610 3910 3610 2530 2440 3650 3340 5050 4410 5370 4690 7510 7280 2590 7020 6490 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Fast PD Exit Slow PD Exit Notes
Data Sheet E1306E30 (Ver. 3.0)
19
EBJ82HF4B1RA
AC Timing for IDD Test Conditions For purposes of IDD testing, the following parameters are to be utilized.
DDR3-1066 Parameter CL (IDD) tCK min.(IDD) tRCD min. (IDD) tRC min. (IDD) tRAS min.(IDD) tRP min. (IDD) tFAW (IDD) tRRD (IDD) tRFC (IDD) 7-7-7 7 1.875 13.13 50.63 37.5 13.13 37.5 7.5 110 DDR3-800 6-6-6 6 2.5 15 52.5 37.5 15 40 10 110 Unit tCK ns ns ns ns ns ns ns ns
DC Characteristics 2 (TC = 0C to +85C, VDD, VDDQ = 1.5V 0.075V) (DDR3 SDRAM Component Specification)
Parameter Input leakage current Output leakage current Symbol ILI ILO Value 2 5 Unit A A Notes VDD VIN VSS DDQ VOUT VSS
Data Sheet E1306E30 (Ver. 3.0)
20
EBJ82HF4B1RA
Pin Functions
CK, /CK (input pin) CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). /CS (input pin) All commands are masked when /CS is registered high. /CS provides for external rank selection on systems with multiple ranks. /CS is considered part of the command code. /RAS, /CAS, and /WE (input pins) /RAS, /CAS and /WE (along with /CS) define the command being entered. A0 to A15 (input pins) Provided the row address for active commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (A10(AP) and A12(/BC) have additional functions, see below) The address inputs also provide the op-code during mode register set commands. [Address Pins Table]
Address (A0 to A13) Row address (RA) AX0 to AX13 Column address (CA) AY0 to AY9, A11 Notes
A10(AP) (input pin) A10 is sampled during read/write commands to determine whether auto-precharge should be performed to the accessed bank after the read/write operation. (high: auto-precharge; low: no auto-precharge) A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = low) or all banks (A10 = high). If only one bank is to be precharged, the bank is selected by bank addresses (BA). A12 (/BC) (input pin) A12 is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed. (A12 = high: no burst chop, A12 = low: burst chopped.) BA0 to BA2 (input pins) BA0, BA1 and BA2 define to which bank an active, read, write or precharge command is being applied. BA0 and BA1 also determine if a mode register is to be accessed during a MRS cycle. [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 L H L H L H L H BA1 L L H H L L H H BA2 L L L L H H H H
Remark: H: VIH. L: VIL.
Data Sheet E1306E30 (Ver. 3.0)
21
EBJ82HF4B1RA
CKE (input pin) CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides precharge power-down and self-refresh operation (all banks idle), or active power-down (row active in any bank). CKE is asynchronous for self-refresh exit. After VREF has become stable during the power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, /CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self-refresh. DQ and CB (input and output pins) Bi-directional data bus. DQS and /DQS (input and output pin) Output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS is paired with differential signals /DQS to provide differential pair signaling to the system during READs and WRITEs. ODT (input pins) ODT (registered high) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS, DM. The ODT pin will be ignored if the mode register (MR1) is programmed to disable ODT. VDD (power supply pins) 1.5V is applied. (VDD is for the internal circuit.) VDDSPD (power supply pin) 3.3V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected. VTT (power supply pin) Termination supply. VREFDQ (power supply) Reference voltage for DQ. VREFCA (power supply) Reference voltage for CA. SCL (input pin) Clock input for serial PD. SDA (input and output pins) Data input/output for serial PD. SA (input pin) Serial address input. /RESET (input pin) /RESET is negative active signal (active low) and is referred to GND.
Data Sheet E1306E30 (Ver. 3.0)
22
EBJ82HF4B1RA
Par_In (input pin) Parity bit for the Address and Control bus. /Err_Out (output pin) Parity error found on the Address and Control bus. /Event (output pin) Temperature alert output.
Detailed Operation Part, Electrical Characteristics and Timing Waveforms
Refer to the EDJ1104BASE, EDJ1108BASE, EDJ1116BASE datasheet (E1128E). DM pins of component device fixed to VSS level on the module board. DIMM /CAS latency = component CL + 1 for registered type.
Data Sheet E1306E30 (Ver. 3.0)
23
EBJ82HF4B1RA
Physical Outline
Unit: mm
Front side
8.50 max
(DATUM -A-)
(Front)
1
120
B
A
47.00
133.35
71.00
1.27 0.10
Back side
9.50
121
240
17.30
4.00 min
DIMM heat spreader
DIMM heat spreader
(Back)
C
Detail A
Detail B
Detail C
(DATUM -A-)
2.50 0.20
1.00
0.20 0.15
(R0.65)
2.50
R0.75
0.80 0.05
3.80
5.00
1.50 0.10
ECA-TS2-0245-02
Data Sheet E1306E30 (Ver. 3.0)
24
3.00
2.10 0.15
30.50 max
EBJ82HF4B1RA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Data Sheet E1306E30 (Ver. 3.0)
25
EBJ82HF4B1RA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Be aware that this product is for use in typical electronic equipment for general-purpose applications. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] Usage in environments with special characteristics as listed below was not considered in the design. Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. Example: 1) Usage in liquids, including water, oils, chemicals and organic solvents. 2) Usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 , SO 2 , and NO x . 4) Usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) Usage in places where dew forms. 6) Usage in environments with mechanical vibration, impact, or stress. 7) Usage near heating elements, igniters, or flammable items. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0706
Data Sheet E1306E30 (Ver. 3.0)
26

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